1. Field of the Invention
The present invention relates to a logic circuit designing method, and more particularly, to a method for designing high-performance logic circuits within a shorter period.
2. Description of Related Art
At present, the most generally used method for designing logic circuits is such that logic functions on a register transfer level or behavior level are described in a Hardware Description Language (HDL) and the logic described on these levels is converted to logic on the gate level by using a logic synthesis CAD tool. Circuit elements called xe2x80x9ccellsxe2x80x9d (generally, a cell having a primitive logic function such as AND, OR, etc.) are pre-designed and the logic synthesis CAD tool is provided with a library in which the designed cells are stored with cell performance parameters such as logic function, layout size, delay, power consumption, etc. By assigning the cells from the library to the logic functions described on the register transfer level or behavior level, a logic circuit (gate level netlist) described in view of cell-to-cell connection is generated from the logic functions described on the register transfer level or behavior levels. The gate level netlist is then passed to a further design process, namely, a layout process.
During the above logic synthesis process, synthesis constraints are given when the cells from the library are assigned to the logic functions. First, constraints of logic circuit design specifications; that is, target values of circuit area, operating speed, power consumption, etc. are given. A logic circuit configuration must be set up to fulfill these constraints. Secondly, external constraints to a logic circuit are given. The external constraints includes: e.g., load capacitance of a cell for driving an input port of the logic circuit to be generated by logic synthesis, load capacitance of a wire or cell connected to an output port of the logic circuit, time at which a signal arrives at the input port, time required for a signal from the output port to pass before arriving at an external flip-flop. Thirdly, wire load constraints assumed for the laid-out logic circuit are given. For example, a wire load assumed, based on a virtual wire load model is given as load capacitance per fan-out.
To summarize the above, the logic synthesis process is supplied with a logic circuit netlist described in HDL, synthesis constraints, and cell library, optimizing the logic structure and assigning the cells to the logic functions are executed during the process, and a gate level netlist of logic circuit is output from the process. Hereon, designing a logic circuit on the register transfer level or behavior level is normally aimed at implementing target logic functions. In most cases, sufficient attention is not paid to physical performance parameters, such as circuit area, operating speed, power consumption, etc. after the logic circuit is implemented with actual semiconductor elements. Consequently, modifying the HDL description, executing the logic synthesis, and evaluating the parameters such as circuit area, operating speed, power consumption, etc. in the gate level netlist generated as the result of the logic synthesis, are repeated so that target specifications are attained.
Even if this logic synthesis process starts, supplied with the same source file described in HDL, the result of logic synthesis, the performance of the generated logic circuit varies, depending on the expertise of synthesis, e.g., what logic synthesis CAD tool is used, how to use the logic synthesis CAD tool, and what synthesis constraints are set. Moreover, if different cell libraries are supplied, naturally, different gate level netlists having different values of performance parameters are output.
With a rapid advance of recent semiconductor technology, the logic circuit scale mountable on a semiconductor chip has increased. On the other hand, logic circuit designers encountered a problem that possible logic design scale does not catch up with the increase of circuit scale. Consequently, logic circuit designers reuse circuit property of a logic circuit that has been designed and used to solve this problem, which appears to be a new trend.
Because logic circuits described in the above-mentioned HDL are independent of semiconductor process and technology, a logic circuit on the register transfer level or behavior level, even if its design is intended for, for example, 0.3 xcexcm generation, can be applied as is to designing semiconductor chips of 0.2 xcexcm process. Such reuse of design property is carried out not only internally within a semiconductor products manufacturer. Distribution of design property among semiconductor products manufacturers by networking also begins; thereby, one manufacturer reuses a logic circuit designed by another manufacturer for designing its semiconductor chips. Design property of pre-designed logic circuits is called Intellectual Property (IP).
With a remarkable advance of digital information processing equipment, typically personal computers, the performance requirements of semiconductor chips rapidly augment year by year. Operating frequency over 1 GHs is required and for semiconductor chips to be mounted on mobile communications equipment driven by battery power, such as portable telephones, reduced power consumption requirement for longer battery life is significant. Logic circuits must be designed to meet these more strict requirements as specifications thereof. Even if the design period on the HDL description level can be cut down by means of design property distribution over a network, the design period of the logic synthesis process will be longer due to meeting more strict requirements. Consequently, a problem arises that the period of designing a semiconductor chip as a whole cannot be cut sufficiently. As a typical example, to attain the target operating frequency of a semiconductor chip, it is necessary to set the delay of all signal paths in the logic circuits on the chip to fall within target cycles of delay. If only one signal path exists that contravenes delay limit requirement, the target frequency cannot be attained. Thus, logic circuit delay design takes the longest design period among the phases of the logic synthesis process. The semiconductor chip design period depends on whether the design team has high-level skill and expertise of delay design.
In the present invention, a logic circuit design method and system are offered in which logic circuits of desired performance can be designed within a shorter period, without increasing the logic design period to fulfill the requirements of circuit area, operating speed, power consumption, etc. as target specifications. Particularly, a logic circuit design method and system are provided for shortening the design period in phases of designing detailed gate level netlists after designing logic circuits on the register transfer level or behavior level, described in HDL,
Heretofore, logic circuits described in HDL have been recognized as design property and logic circuit designers have practiced using IP held by someone else in designing their products. However, if the logic synthesis ability is insufficient as described above, the overall design capability cannot be enhanced even if only the logic circuits described in HDL are distributed over a network. Addressing this problem, in the present invention wherein such detailed design skill, particularly, a logic synthesis design skill is considered as one property, a logic circuit design method and system are provided by making effective use of a design skill attained and possessed by someone else as IP when designing semiconductor chips.
By applying the present invention, logic circuit designers can make effective use of a design skill attained and possessed by someone else as IP when designing semiconductor chips so that a semiconductor chip design process as a whole will be made efficient.
In the present invention, one party at a first design site who designed a circuit with logic functions on the register transfer level or behavior level and performed logic synthesis on the circuit, but could not attain desired circuit performance requests another party at a second design site to perform logic synthesis processing again. After the processing, a design charge shall be paid to the party at the second design site, depending on the improvement made to the performance of the gate level logic circuit generated at the first design site. Prior to the request, both parties at the first and second sites must agree about the performance parameters of the gate level logic circuit generated at the first design site.
The first design site and the second design site are connected by a network and information for design, such as a logic circuit, library, logic synthesis CAD tool (program), etc. is transferred to the first site. Notwithstanding that an optical or magnetic recording medium can be used to send data files, quick information transfer over the network especially serves the purpose of cutting the design period.
The party at the second design site can use its proprietary circuit construction technique or IP to generate a gate level logic circuit. If the party of the second design site generates a gate level logic circuit, using IP that is not held by the party at the first site, it must offer the information about the IP to the party at the first site.
If the party at the second design site employs a logic synthesis CAD tool to generate a gate level logic circuit, it can license the party at the first design site to use the logic synthesis CAD tool in designing the logic circuit.
For this limited licensing, it is necessary to limit the program operation to a specific object. Thus, the program comprises a processing (logic synthesis) subprogram to be executed to perform predetermined processing, a feature extraction subprogram for extracting the features of an input object to identify the object for which the processing program can be executed to perform the processing, and an execution enable/disable judgment subprogram to judge whether to enable or disable the processing execution by comparing the features of the object permitted to undergo the logic synthesis and the features extracted from the input object by the feature extraction subprogram. If this program structure applies to the logic synthesis CAD tool, it is desirable to use information that seldom changes throughout a design period as the features of the object (i.e., logic circuit).
Semiconductor manufacturers have lately been and are practicing actively logic circuit design (IP) distribution over a network. Even if such IP distribution is used, the purchaser of the IP must execute logic synthesis on an RTL logic circuit to output a gate level logic circuit. However, the circuit performance attained varies considerably, depending on whether the logic synthesis is good or bad as noted above. Addressing this, the present invention is preferably embodied such that the logic synthesis CAD tool employed by the IP seller can be used with the distributed logic circuit. Consequently, the logic synthesis executed by the IP seller can also be executed on the purchaser side. With this manner of embodiment, it is desirable to apply the above-described program structure to limit the use of the logic synthesis CAD tool to the IP.
Other and further objects, features and advantages of the invention will appear more fully from the following description.